Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10083728 | Memory controller, memory module and memory system | Yan Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Chih-Chien Hung, Shang-Pin Chen | 2018-09-25 |
| 9557764 | Clock tree circuit and memory controller | Chen-Feng Chiang, Kai Chen, Chih-Tsung Yao | 2017-01-31 |
| 9256245 | Clock tree circuit and memory controller | Chen-Feng Chiang, Kai Chen, Chih-Tsung Yao | 2016-02-09 |
| 8952718 | Termination circuit and DC balance method thereof | Yan Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Chih-Chien Hung, Shang-Ping Chen | 2015-02-10 |
| 7779215 | Method and related apparatus for accessing memory | Bowei Hsieh, Jiin Lai | 2010-08-17 |
| 7610454 | Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses | — | 2009-10-27 |
| 7573759 | Method for detecting data strobe signal | Bo-Wei Hsieh, Weber Chuang, Chi Chang | 2009-08-11 |
| 7552292 | Method of memory space configuration | Bo-Wei Hsieh | 2009-06-23 |
| 7444535 | Method and related apparatus for adjusting timing of memory signals | Bowei Hsieh | 2008-10-28 |
| 7418617 | Apparatus for adjusting timing of memory signals | Bowei Hsieh | 2008-08-26 |
| 7382665 | Method for detecting data strobe signal | Bo-Wei Hsieh, Weber Chuang, Chi Chang | 2008-06-03 |
| 7257035 | Method for detecting data strobe signal | Bo-Wei Hsieh, Weber Chuang, Chi Chang | 2007-08-14 |
| 7206917 | Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses | — | 2007-04-17 |
| 7133790 | Method and system of calibrating the control delay time | — | 2006-11-07 |
| 6915226 | Method and system of calibrating the control delay time | — | 2005-07-05 |
| 6760263 | Method and device for controlling data latch time | — | 2004-07-06 |