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Method and system for high speed data links |
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Adaptive routing for link-level retry protocol |
Russell L. Nicol, Joseph M. Placek |
2019-03-26 |
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Packet-based adaptive forward error correction |
Frank R. Dropps |
2019-03-05 |
| 9852096 |
High speed serial link in-band lane fail over for RAS and power management |
John Francis De Ryckere, Joseph M. Placek, Karen Rae Beighley |
2017-12-26 |
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Low latency serial data encoding scheme for enhanced burst error immunity and long term reliability |
John Francis De Ryckere |
2016-02-02 |
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Interface for synchronous data transfer between domains clocked at different frequencies |
William A. Huffman, Vernon W. Swanson, Nan Ma, Randal S. Passint |
2008-02-19 |
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Dual-bank FIFO for synchronization of read data in DDR SDRAM |
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2005-07-19 |
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Memory daughter card apparatus, configurations, and methods |
Stephen Cermak, III, Jeffrey S. Conger, David Paul Gruber, Thomas Alex Crapisi, Stephen A. Bowen +1 more |
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Discrete delay line system and method |
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2003-02-11 |
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System and method for accurate adjustment of discrete integrated circuit delay lines |
— |
2002-12-17 |
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System and method for generating clock signals |
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2002-08-27 |
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Method and apparatus for adjusting the power supply voltage provided to a microprocessor |
Richard B. Salmonson, Robert Greener, Robert James Lutz, Max C. Logan, Richard G. Finstad |
1997-12-02 |
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Bipolar ECL to inverted CMOS level translator |
Terrance L. Bowman |
1995-06-13 |
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Repetitive signal detector for preventing thermal runaway |
Mario J. Rizzo |
1995-05-23 |
| 5329188 |
Clock pulse measuring and deskewing system and process |
Kenneth A. Van Goor, Gregory Roy Edlund, Arthur H. Orth |
1994-07-12 |