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Programmable hardware scheduler for digital processing systems |
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Method and apparatus for load balancing of jobs scheduled for processing |
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Long path at-speed testing |
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Unified memory system for multiple processors and method for controlling the same |
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Low power, variable precision DDA for 3D graphics applications |
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Method and system for improving noise margin in a receiver circuit |
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Cache controller with improved instruction and data forwarding during refill operation |
— |
2000-06-13 |
