Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6365449 | Process for making a non-volatile memory cell with a polysilicon spacer defined select gate | Etan Shacham | 2002-04-02 |
| 6063667 | Method for reducing the capacitance across the layer of tunnel oxide of an electrically-erasable programmable read-only-memory cell | — | 2000-05-16 |
| 6060895 | Wafer level dielectric test structure and related method for accelerated endurance testing | Sik-Han Soh | 2000-05-09 |
| 5844269 | EEPROM cell having reduced capacitance across the layer of tunnel oxide | — | 1998-12-01 |
| 5576988 | Secure non-volatile memory array | James M. Jaffe | 1996-11-19 |
| 5475251 | Secure non-volatile memory cell | James M. Jaffe | 1995-12-12 |