Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4825438 | Bus error detection employing parity verification | Donald B. Bennett, Thomas W. Petschauer | 1989-04-25 |
| 4734909 | Versatile interconnection bus | Donald B. Bennett, Thomas W. Petschauer | 1988-03-29 |
| 4500988 | VLSI Wired-OR driver/receiver circuit | Donald B. Bennett, Thomas W. Petschauer | 1985-02-19 |
| 4477904 | Parity generation/detection logic circuit from transfer gates | — | 1984-10-16 |
| 4234934 | Apparatus for scaling memory addresses | — | 1980-11-18 |
| 4227244 | Closed loop address | Gary A. Spencer | 1980-10-07 |
| 4223382 | Closed loop error correct | — | 1980-09-16 |