LW

Larry Widigen

AM AMD: 16 patents #689 of 9,279Top 8%
NA Nexgen Ag: 4 patents #1 of 14Top 8%
Overall (All Time): #226,200 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6671798 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2003-12-30
6360318 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2002-03-19
6282639 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2001-08-28
6195745 Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 2001-02-27
6108777 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2000-08-22
6041396 Segment descriptor cache addressed by part of the physical address of the desired descriptor — 2000-03-21
5923579 Optimized binary adder and comparator having an implicit constant for an input Elliot A. Sowadsky 1999-07-13
5919256 Operand cache addressed by the instruction address for reducing latency of read instruction Elliot A. Sowadsky 1999-07-06
5822786 Apparatus and method for determining if an operand lies within an expand up or expand down segment Elliot A. Sowadsky 1998-10-13
5815699 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 1998-09-29
5802339 Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 1998-09-01
5699279 Optimized binary adders and comparators for inputs having different widths Elliot A. Sowadsky 1997-12-16
5675758 Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 1997-10-07
5623614 Branch prediction cache with multiple entries for returns having multiple callers Korbin S. Van Dyke, David L. Puziol 1997-04-22
5590351 Superscalar execution unit for sequential instruction pointer updates and segment limit checks Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 1996-12-31
5583806 Optimized binary adder for concurrently generating effective and intermediate addresses William A. Stutz 1996-12-10
5517440 Optimized binary adders and comparators for inputs having different widths Elliot A. Sowadsky 1996-05-14
5454117 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 1995-09-26
5418736 Optimized binary adders and comparators for inputs having different widths Elliot A. Sowadsky 1995-05-23
5394351 Optimized binary adder and comparator having an implicit constant for an input Elliot A. Sowadsky 1995-02-28