KD

Kieu Do

BS Breker Verification Systems: 12 patents #2 of 5Top 40%
VT Vlsi Technology: 2 patents #227 of 594Top 40%
Overall (All Time): #342,304 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11748240 Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2023-09-05
11113184 Display in a graphical format of test results generated using scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2021-09-07
11055212 Testing SoC with portable scenario models and at different levels Adnan Hamid, Kairong Qian, Joerg Grosse 2021-07-06
10838006 Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2020-11-17
10429442 Testing SOC with portable scenario models and at different levels Adnan Hamid, Kairong Qian, Joerg Grosse 2019-10-01
10365326 Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2019-07-30
9874608 Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2018-01-23
9689921 Testing SoC with portable scenario models and at different levels Adnan Hamid, Kairong Qian, Joerg Grosse 2017-06-27
9651619 Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2017-05-16
9360523 Display in a graphical format of test results generated using scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2016-06-07
9316689 Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models Adnan Hamid, Kairong Qian, Joerg Grosse 2016-04-19
9310433 Testing SOC with portable scenario models and at different levels Adnan Hamid, Kairong Qian, Joerg Grosse 2016-04-12
5399517 Method of routing three layer metal gate arrays using a channel router Sunil Ashtaputre, Mark R. Hartoog, Prasad Sakhamuri, Charles H Ng 1995-03-21
5353235 Wire length minimization in channel compactor Sunil Ashtaputre 1994-10-04