JK

John C. Kriz

AS Agere Systems: 29 patents #15 of 1,849Top 1%
LS Lsi: 8 patents #151 of 1,740Top 9%
AT AT&T: 1 patents #10,626 of 18,772Top 60%
AG Agere Systems Guardian: 1 patents #274 of 810Top 35%
Overall (All Time): #80,038 of 4,157,543Top 2%
40
Patents All Time

Issued Patents All Time

Showing 25 most recent of 40 patents

Patent #TitleCo-InventorsDate
8598941 Hybrid impedance compensation in a buffer circuit Dipankar Bhattacharya, Ashish V. Shukla, Makeshwar Kothandaraman, Pankaj Kumar, Pramod Elamannu Parameswaran 2013-12-03
8536925 Voltage level translator circuit Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris, Jeffrey J. Nagy, Peter James Nicholas 2013-09-17
8441281 Current-mode logic buffer with enhanced output swing Makeshwar Kothandaraman, Pankaj Kumar, Paul Hartley 2013-05-14
8362803 Mode latching buffer circuit Peter James Nicholas, Dipankar Bhattacharya, James John Bradley 2013-01-29
8159262 Impedance compensation in a buffer circuit Dipankar Bhattacharya, Ashish V. Shukla, Makeshwar Kothandaraman 2012-04-17
8130030 Interfacing between differing voltage level requirements in an integrated circuit system Pankaj Kumar, Pramod Elamannu Parameswaran, Makeshwar Kothandaraman, Vani Deshpande 2012-03-06
8125267 Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation Pankaj Kumar, Pramod Elamannu Parameswaran, Makeshwar Kothandaraman, Vani Deshpande 2012-02-28
8089739 Electrostatic discharge protection circuit Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris, Yehuda Smooha 2012-01-03
7936209 I/O buffer with low voltage semiconductor devices Dipankar Bhattacharya, Makeshwar Kothandaraman, Jeffrey J. Nagy, Yehuda Smooha, Pankaj Kumar 2011-05-03
7902904 Bias circuit scheme for improved reliability in high voltage supply with low voltage device Pankaj Kumar, Makeshwar Kothandaraman, Dipankar Bhattacharya, Jeffrey J. Nagy, Pramod Elamannu Parameswaran 2011-03-08
7876132 Floating well circuit operable in a failsafe condition and a tolerant condition Pankaj Kumar, Pramod Elamannu Parameswaran, Makeshwar Kothandaraman, Vani Deshpande 2011-01-25
7869300 Memory device control for self-refresh mode Dharmeshkumar N. Bhakta, Eric PERSSON 2011-01-11
7642807 Multiple-mode compensated buffer circuit Dipankar Bhattacharya, Gregg R. Harleman, Makeshwar Kothandaraman, Bernard L. Morris 2010-01-05
7551020 Enhanced output impedance compensation Dipankar Bhattacharya, Makeshwar Kothandaraman, Antonio M. Marques, Bernard L. Morris 2009-06-23
7529070 Power pin to power pin electro-static discharge (ESD) clamp Dipankar Bhattacharya, Che Leung, Duane J. Loeper, Yehuda Smooha 2009-05-05
7529071 Circuit for selectively bypassing a capacitive element Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris, Yehuda Smooha 2009-05-05
7511550 Method and apparatus for improving reliability of an integrated circuit having multiple power domains Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris, Yehuda Smooha 2009-03-31
7498860 Buffer circuit having multiplexed voltage level translation Dipankar Bhattacharya, Carol Ann Huber, Makeshwar Kothandaraman, Bernard L. Morris 2009-03-03
7495873 Electrostatic discharge protection in a semiconductor device Dipankar Bhattacharya, Bernard L. Morris, Yehuda Smooha 2009-02-24
7432762 Circuit having enhanced input signal range Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris 2008-10-07
7430100 Buffer circuit with enhanced overvoltage protection Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris 2008-09-30
7397279 Voltage level translator circuit with wide supply voltage range Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris, Joseph E. Simko 2008-07-08
7391825 Comparator circuit having reduced pulse width distortion Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris 2008-06-24
7382168 Buffer circuit with multiple voltage range Dipankar Bhattacharya, Makeshwar Kothandaraman, Bernard L. Morris, Yehuda Smooha 2008-06-03
7276957 Floating well circuit having enhanced latch-up performance Dipankar Bhattacharya, Makeshwar Kothandaraman, Duane J. Loeper, Bernard L. Morris, Yehuda Smooha 2007-10-02