Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6408008 | Circuit for attenuation of echos caused by line variations and an interfacing system for capacitively coupling a plurality of sources to a two-wire communication line | Jack L. Minney, Stephen P. Nordine, Harold F. Lewis, Richard Wada, John F. Stockman | 2002-06-18 |
| 6018219 | Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same | Jack L. Minney, Stephen P. Nordine, Harold F. Lewis, Richard Wada, John F. Stockman | 2000-01-25 |
| 6002618 | NMOS input receiver circuit | Clarence W. Padgett, Scott B. Tanner, Shin-ichi Kojima, Jack L. Minney, Motohiro Oishi +2 more | 1999-12-14 |
| 5959413 | Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same | Jack L. Minney, Stephen P. Nordine, Harold F. Lewis, Richard Wada, John F. Stockman | 1999-09-28 |
| 5907517 | Memory circuit yield generator and timing adjustor | Clarence W. Padgett | 1999-05-25 |
| 5870346 | VLSI memory circuit | Clarence W. Padgett, Scott B. Tanner, Shin-ichi Kojima, Jack L. Minney, Motohiro Oishi +2 more | 1999-02-09 |
| 5825777 | Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same | Jack L. Minney, Stephen P. Nordine, Harold F. Lewis, Richard Wada, John F. Stockman | 1998-10-20 |
| 5812461 | Driver circuit for addressing core memory and a method for the same | Clarence W. Padgett, Robert D. Amneus, Scott B. Tanner | 1998-09-22 |
| 5793698 | Semiconductor read-only VLSI memory | Scott B. Tanner, Clarence W. Padgett, Jack L. Minney | 1998-08-11 |
| 5732035 | Very large scale integrated planar read only memory | Clarence W. Padgett | 1998-03-24 |
| 5650979 | Semiconductor read-only VLSI memory | Scott B. Tanner, Clarence W. Padgett, Jack L. Minney | 1997-07-22 |
| 5608687 | Output driver control for ROM and RAM devices | Clarence W. Padgett, Scott B. Tanner, Shin-ichi Kojima, Jack L. Minney, Motohiro Oishi +2 more | 1997-03-04 |
| 5596544 | Very large scale integrated planar read only memory | Clarence W. Padgett, Scott B. Tanner, Jack L. Minney | 1997-01-21 |
| 5594696 | Improvemetns in a detection circuit with a level shifting circuit | Clarence W. Padgett, Robert D. Amneus, Scott B. Tanner | 1997-01-14 |
| 5581203 | Semiconductor read-only VLSI memory | Scott B. Tanner, Clarence W. Padgett, Jack L. Minney | 1996-12-03 |
| 5548592 | Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same | Jack L. Minney, Stephen P. Nordine, Harold F. Lewis, Richard Wada, John F. Stockman | 1996-08-20 |
| 5487038 | Method for read cycle interrupts in a dynamic read-only memory | Clarence W. Padgett, Scott B. Tanner, Shin-ichi Kojima, Jack L. Minney, Motohiro Oishi +2 more | 1996-01-23 |
| 5467300 | Grounded memory core for Roms, Eproms, and EEpproms having an address decoder, and sense amplifier | Clarence W. Padgett, Robert D. Amneus, Scott B. Tanner | 1995-11-14 |
| 5459693 | Very large scale integrated planar read only memory | Clarence W. Padgett, Scott B. Tanner, Jack L. Minney | 1995-10-17 |
| 5414663 | VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines | Scott B. Tanner, Clarence W. Padgett, Jack L. Minney | 1995-05-09 |
| 5241497 | VLSI memory with increased memory access speed, increased memory cell density and decreased parasitic capacitance | — | 1993-08-31 |