IG

Ilie Garbacea

OV Ovics: 6 patents #2 of 2Top 100%
Apple: 4 patents #6,306 of 18,612Top 35%
MP Maxim Integrated Products: 4 patents #200 of 945Top 25%
GS Geo Semiconductor: 2 patents #10 of 25Top 40%
MT Mips Technologies: 1 patents #18 of 35Top 55%
Overall (All Time): #273,260 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11211036 Timestamp based display update mechanism Brijesh Tripathi, Arthur L. Spence, Joshua P. de Cesare, Guy Cote, Mahesh B. Chappalli +2 more 2021-12-28
10706825 Timestamp based display update mechanism Brijesh Tripathi, Arthur L. Spence, Joshua P. de Cesare, Guy Cote, Mahesh B. Chappalli +2 more 2020-07-07
10534614 Rescheduling threads using different cores in a multithreaded microprocessor having a shared register pool 2020-01-14
10535287 Step-down pixel response correction systems and methods Chaohao Wang, Lu Zhang, Zhibing Ge, Shih-Chyuan Fan Jiang, Marc Albrecht +6 more 2020-01-14
10410587 Display pixel charge accumulation compensation systems and methods Chaohao Wang, Chengrui Le 2019-09-10
9280513 Matrix processor proxy systems and methods Sorin C. Cismas 2016-03-08
8831093 Video encoding control using non-exclusive content categories Lulin Chen, Jose R. Alvarez 2014-09-09
8640129 Hardware multithreading systems and methods Sorin C. Cismas, Kristan J. Monsen 2014-01-28
8327114 Matrix processor proxy systems and methods Sorin C. Cismas 2012-12-04
8149909 Video encoding control using non-exclusive content categories Lulin Chen, Jose R. Alvarez 2012-04-03
8145880 Matrix processor data switch routing systems and methods Sorin C. Cismas 2012-03-27
8131975 Matrix processor initialization systems and methods Sorin C. Cismas 2012-03-06
8126283 Video encoding statistics extraction using non-exclusive content categories Lulin Chen, Jose R. Alvarez 2012-02-28
8094716 Method and apparatus of adaptive lambda estimation in Lagrangian rate-distortion optimization for video coding Lulin Chen 2012-01-10
7958341 Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory Sorin C. Cismas 2011-06-07
7870365 Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel Sorin C. Cismas 2011-01-11
7765547 Hardware multithreading systems with state registers having thread profiling data Sorin C. Cismas, Kristan J. Monsen 2010-07-27