Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5924127 | Address translation buffer system and method for invalidating address translation buffer, the address translation buffer partitioned into zones according to a computer attribute | Koji Kawamoto, Kuniki Tohbaru | 1999-07-13 |
| 5490259 | Logical-to-real address translation based on selective use of first and second TLBs | Tohru Hiraoka, Akira Yamaoka | 1996-02-06 |
| 4783783 | Data processing system having pipeline arithmetic/logic units | Seiji Nagai, Takaaki Nishiyama, Fujio Wakui | 1988-11-08 |