Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11093286 | Computing device with resource manager and civilware tier | — | 2021-08-17 |
| 11062068 | Electronic computer-aided design tool | — | 2021-07-13 |
| 10810010 | Enhanced security computer processor with mentor circuits | — | 2020-10-20 |
| 10140122 | Computer processor with operand/variable-mapped namespace | — | 2018-11-27 |
| 10095641 | Processor with frames/bins structure in local high speed memory | — | 2018-10-09 |
| 10067878 | Processor with logical mentor | — | 2018-09-04 |
| 10061511 | Computing device with frames/bins structure, mentor layer and plural operand processing | — | 2018-08-28 |
| 9984186 | Electronic computer-aided design tool | — | 2018-05-29 |
| 9977693 | Processor that uses plural form information | — | 2018-05-22 |
| 6340588 | Matrices with memories | Michael Nova | 2002-01-22 |
| 6329139 | Automated sorting system for matrices with memory | Michael Nova, John E. Lillig, Kanchana Sanjaya Gunesekera Karunaratne, William Ewing, Yozo Satoda | 2001-12-11 |
| 6319668 | Method for tagging and screening molecules | Michael Nova, Xiao-Yi Xiao, Zahra Parandoosh, Gary S. David | 2001-11-20 |
| 6284459 | Solid support matrices with memories and combinatorial libraries therefrom | Michael Nova, Andrew E. Senyei, Xiao-Yi Xiao, Chanfeng Zhao | 2001-09-04 |
| 6100026 | Matrices with memories and uses thereof | Michael Nova, Andrew E. Senyei | 2000-08-08 |
| 6017496 | Matrices with memories and uses thereof | Michael Nova, Zahra Parandoosh, Andrew E. Senyei, Xiao-Yi Xiao, Gary S. David +2 more | 2000-01-25 |
| 5961923 | Matrices with memories and uses thereof | Michael Nova, Zahra Parandoosh, Andrew E. Senyei, Xiao-Yi Xiao, Gary S. David +2 more | 1999-10-05 |
| 5296722 | Electrically alterable resistive component stacked above a semiconductor substrate | Melvyn E. Genter, Bruce B. Roesner | 1994-03-22 |
| 5148256 | Digital computer having an interconnect mechanism stacked above a semiconductor substrate | Melvyn E. Genter, Bruce B. Roesner | 1992-09-15 |
| 4933735 | Digital computer having control and arithmetic sections stacked above semiconductor substrate | Burton L. Levin, Bruce B. Roesner | 1990-06-12 |
| 4837730 | Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations | Erick M. Cook, Andrew Everett Phelps | 1989-06-06 |
| 4777615 | Backplane structure for a computer superpositioning scalar and vector operations | — | 1988-10-11 |
| 4760518 | Bi-directional databus system for supporting superposition of vector and scalar operations in a computer | Erick M. Cook, Andrew Everett Phelps, Mark A. Haakmeester, Jennifer S. Schuh, William B. Thompson | 1988-07-26 |
| 4744024 | Method of operating a bus in a data processing system via a repetitive three stage signal sequence | Melvyn E. Genter | 1988-05-10 |
| 4538241 | Address translation buffer | Burton L. Levin, Andrew Everett Phelps | 1985-08-27 |
| 4467409 | Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations | Burton L. Levin, Melvyn E. Genter | 1984-08-21 |