HE

Haggai Eran

NV NVIDIA: 12 patents #566 of 7,811Top 8%
IBM: 1 patents #44,794 of 70,183Top 65%
Overall (All Time): #368,939 of 4,157,543Top 9%
13
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12045178 Devices, methods, and systems for disaggregated memory resources in a computing environment Dimitrios Syrivelis, Paraskevas Bakopoulos, Ioannis (Giannis) Patronas, Elad Mentovich, James Stephen Fields, Jr. +1 more 2024-07-23
11991073 Dual software interfaces for multiplane devices to separate network management and communication traffic Inbal Gal, Guy Rozenberg Kunievsky, Jason Gunthorpe, Liran Liss, Vladimir Koushnir 2024-05-21
11757796 Zero-copy processing Liran Liss, Yuval Shpigelman, Idan Burstein 2023-09-12
11693804 Cross bus memory mapping Alex Rosenbaum, Oren Duer, Alexander Mikheev, Nitzan Carmi 2023-07-04
11418454 Computational accelerator for packet payload operations Boris Pismenny, Liran Liss, Ilya Lesokhin, Adi Menachem 2022-08-16
11184439 Communication with accelerator via RDMA-based network adapter Dotan David Levi, Maxim Fudim, Liran Liss 2021-11-23
11005771 Computational accelerator for packet payload operations Boris Pismenny, Liran Liss, Ilya Lesokhin, Adi Menachem 2021-05-11
10841243 NIC with programmable pipeline Dotan David Levi, Liran Liss, Noam Bloch, Idan Burstein, Lior Narkis +1 more 2020-11-17
10218645 Low-latency processing in a network node Shachar Raindel, Yaniv Saar, Yishai Israel Hadas, Ari Zigler 2019-02-26
9639464 Application-assisted handling of page faults in I/O operations Shachar Raindel, Liran Liss, Noam Bloch 2017-05-02
8914458 Look-ahead handling of page faults in I/O operations Shachar Raindel, Liran Liss, Noam Bloch 2014-12-16
8745276 Use of free pages in handling of page faults Noam Bloch, Shachar Raindel, Liran Liss 2014-06-03
8234615 Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout Shyam Ramji, Bella Dubrov, Ari Freund, Edward F. Mark, Timothy A. Schell 2012-07-31