Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6074429 | Optimizing combinational circuit layout through iterative restructuring | Satyamurthy Pullela, Stephen C. Moore, David Theodore Blaauw, Rajendran Panda | 2000-06-13 |
GV
Gopalakrishnan Vijayan
Overall (All Time): #3,617,819 of 4,157,543Top 90%
1
Patents All Time