Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6630381 | Preventing dielectric thickening over a floating gate area of a transistor | — | 2003-10-07 |
| 6136652 | Preventing dielectric thickening over a channel area of a split-gate transistor | — | 2000-10-24 |
| 5784327 | Memory cell array selection circuits | — | 1998-07-21 |
| 5677867 | Memory with isolatable expandable bit lines | — | 1997-10-14 |
| 5659514 | Memory cell and current mirror circuit | — | 1997-08-19 |
| 5535167 | Non-volatile memory circuits, architecture | — | 1996-07-09 |
| 5440518 | Non-volatile memory circuits, architecture and methods | — | 1995-08-08 |
| 5332914 | EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells | — | 1994-07-26 |
| 5304505 | Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells | — | 1994-04-19 |
| 5303185 | EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells | — | 1994-04-12 |
| 5278785 | Non-volatile memory circuits and architecture | — | 1994-01-11 |
| 5247346 | E.sup.2 PROM cell array including single charge emitting means per row | — | 1993-09-21 |
| 5166904 | EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells | — | 1992-11-24 |
| 5162247 | Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array | — | 1992-11-10 |
| 5099297 | EEPROM cell structure and architecture with programming and erase terminals shared between several cells | — | 1992-03-24 |
| 5087583 | Process for EEPROM cell structure and architecture with shared programming and erase terminals | — | 1992-02-11 |
| 5047814 | E.sup.2 PROM cell including isolated control diffusion | — | 1991-09-10 |
| 5040036 | Trench-isolated self-aligned split-gate EEPROM transistor and memory array | — | 1991-08-13 |
| 4845538 | E.sup.2 prom cell including isolated control diffusion | — | 1989-07-04 |
| 4763299 | E.sup.2 PROM cell and architecture | — | 1988-08-09 |