Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5654588 | Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure | Robert W. Bollish, Alfredo Figueroa, James H. Carlquist, Thomas R. Yarbrough, Charles F. Toewe +5 more | 1997-08-05 |
| 5594273 | Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield | Donald R. Kost, Lawrence Day | 1997-01-14 |
| 5504369 | Apparatus for performing wafer level testing of integrated circuit dice | Robert W. Bollish, Alfredo Figueroa, James H. Carlquist, Thomas R. Yarbrough, Charles F. Toewe +4 more | 1996-04-02 |
| 5399505 | Method and apparatus for performing wafer level testing of integrated circuit dice | Robert W. Bollish, Alfredo Figueroa, James H. Carlquist, Thomas R. Yarbrough, Charles F. Toewe +5 more | 1995-03-21 |