Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6107979 | Monolithic programmable format pixel array | Quang Dieu An, Kevin Kornher | 2000-08-22 |
| 5682174 | Memory cell array for digital spatial light modulator | — | 1997-10-28 |
| 5670976 | Spatial light modulator having redundant memory cells | Shigeki Numaga, Takeshi Honzawa | 1997-09-23 |
| 5670977 | Spatial light modulator having single bit-line dual-latch memory cells | Quang Dieu An | 1997-09-23 |
| 5313231 | Color palette device having big/little endian interfacing, systems and methods | Chenwei J. Yin, Richard C. Nail, Louis J. Izzi | 1994-05-17 |
| 5291078 | Gate circuits in transition detection input buffers | Chai-Chin Chao | 1994-03-01 |
| 5222230 | Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges | Michael C. Gill, Henry M. Darley, Jeffrey A. Niehaus | 1993-06-22 |
| 5021994 | Look-ahead flag generator | Jy-Der David Tai, Quang Dieu An, Te-Chuan Hsu | 1991-06-04 |
| 4933901 | Method for assigning priority to read and write requests received closely in time | Jy-Der David Tai | 1990-06-12 |
| 4916651 | Floating point processor architecture | Michael C. Gill, Henry M. Darley, Jeffrey A. Niehaus | 1990-04-10 |
| 4884270 | Easily cascadable and testable cache memory | Roland H. Pang | 1989-11-28 |
| 4860262 | Cache memory reset responsive to change in main memory | — | 1989-08-22 |
| 4858182 | High speed zero power reset circuit for CMOS memory cells | Roland H. Pang | 1989-08-15 |
| 4837743 | Architecture for memory multiplexing | Jy-Der David Tai, Te-Chuan Hsu | 1989-06-06 |
| 4831625 | Easily cascadable and testable cache memory | Roland H. Pang | 1989-05-16 |
| 4815039 | Fast real-time arbiter | Jy-Der David Tai | 1989-03-21 |
| 4789793 | Integrated FET circuit to reduce switching noise | George J. Ehni, Jy-Der David Tai, Thomas A. Carroll | 1988-12-06 |