DS

David C. Smith

Canon: 7 patents #7,830 of 19,416Top 45%
UA US Army: 4 patents #726 of 6,974Top 15%
Pioneer (Corteva): 2 patents #788 of 1,535Top 55%
RC Rca: 2 patents #592 of 1,739Top 35%
GE: 2 patents #13,562 of 36,430Top 40%
Overall (All Time): #216,712 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12423017 System and method for performing and verifying data erasure Phyllis Tsu, Michael Mercado, Jianning Yue, Samuel Hinkhouse 2025-09-23
8938118 Method of neighbor embedding for OCR enhancement Rajiv Jain 2015-01-20
8705118 Threshold-based load balancing printing system 2014-04-22
8638470 Efficient banded hybrid rendering Thomas Benjamin Sanjay Thomas 2014-01-28
7975632 Seed planter Joseph Kevin Gogerty, Daniel Goldman, Kent Hoeppner, James L. Hunter, Jason J. Kelsick +5 more 2011-07-12
7938075 Automated seed detection and planting synchronization apparatus, method and system Matthew K. Glendenning, Daniel Goldman, David E. Johnson, Jason J. Kelsick 2011-05-10
7755629 Method of rendering graphic objects 2010-07-13
7583397 Method for generating a display list 2009-09-01
7477265 System and method for optimising halftoning printer performance Giles Puckett 2009-01-13
7454337 Method of modeling single data class from multi-class data Daniel J. Richman 2008-11-18
7286142 System and method for optimising halftoning printer performance Giles Puckett 2007-10-23
6891536 Method of determining active priorities 2005-05-10
6212989 High pressure, high temperature window assembly and method of making the same Richard A. Beyer, Gregory Burke, John J. O'Reilly, Henry Kerwien, Mark Todaro 2001-04-10
4962556 Lightweight, collapsible bridge module, and system with deployment and retrieval trailer Richard W. Helmke, Mark P. Levine 1990-10-16
4815003 Structured design method for high density standard cell and macrocell layout of VLSI chips Rathindra N. Putatunda, Stephen A. McNeary 1989-03-21
4811237 Structured design method for generating a mesh power bus structure in high density layout of VLSI chips Rathindra N. Putatunda, Stephen A. McNeary 1989-03-07
4686629 Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit Richard Noto 1987-08-11
4636965 Routing method in computer-aided-customization of universal arrays and resulting integrated circuit Richard Noto 1987-01-13
4613941 Routing method in computer aided customization of a two level automated universal array Richard Noto 1986-09-23
4500963 Automatic layout program for hybrid microcircuits (HYPAR) Richard Noto 1985-02-19