Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8779824 | Clock distribution using MTJ sensing | Wenqing Wu, Kendrick Hoy Leong Yuen, Robert P. Gilmore, Jeff Levin | 2014-07-15 |
| 8750324 | Single wire bus interface | Brett C. Walker, Muhammad Asim Muneer | 2014-06-10 |
| 8661274 | Temperature compensating adaptive voltage scalers (AVSs), systems, and methods | Richard Gerard Hofmann, Richard A. Moore | 2014-02-25 |
| 7814380 | Built-in self test (BIST) architecture having distributed interpretation and generalized command protocol | Roberto Fabian Averbuj | 2010-10-12 |
| 7392442 | Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol | Roberto Fabian Averbuj | 2008-06-24 |
| 7184915 | Tiered built-in self-test (BIST) architecture for testing distributed memory modules | Roberto Fabian Averbuj | 2007-02-27 |
| 6757864 | Method and apparatus for efficiently reading and storing state metrics in memory for high-speed ACS viterbi decoder implementations | — | 2004-06-29 |
| 6519297 | Decoding with partial state information on a convolutionally encoded channel | Brian K. Butler, Gwain Bayley, Edward G. Tiedemann, Jr. | 2003-02-11 |
| 6493354 | Resource allocator | Avneesh Agrawal | 2002-12-10 |
| 6366600 | Spreader architecture for direct sequence spread spectrum communications | Avneesh Agrawal, Paul E. Bender | 2002-04-02 |
| 6333954 | High-speed ACS for Viterbi decoder implementations | — | 2001-12-25 |
| 6278715 | System and method for reducing deinterleaver memory requirements through chunk allocation | — | 2001-08-21 |
| 6269130 | Cached chainback RAM for serial viterbi decoder | — | 2001-07-31 |
| 6205186 | Decoding with partial state information on a convolutionally encoded channel | Brian K. Butler, Gwain Bayley, Edward G. Tiedemann, Jr. | 2001-03-20 |