CL

Ching-Hsiang Lin

GL Genesys Logic: 3 patents #14 of 66Top 25%
NU National Yang Ming Chiao Tung University: 2 patents #38 of 406Top 10%
IT ITRI: 1 patents #5,197 of 9,619Top 55%
VS Vanguard International Semiconductor: 1 patents #340 of 585Top 60%
VT Via Technologies: 1 patents #566 of 1,108Top 55%
Overall (All Time): #493,692 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11822497 USB device, USB cable and USB repeater thereof 2023-11-21
11714771 USB signal transmission device, operation method thereof, and USB cable 2023-08-01
11570063 Quality of experience optimization system and method Ta-Sung Lee, En-Cheng Liou, Yu-Chien Lin, Ting-Yen Kuo 2023-01-31
11558533 Method of reading data and data-reading device 2023-01-17
11533637 High-mobility resource allocation system and method for simulated users Kai-Ten Feng, En-Cheng Liou, Pei-Ying Wu, Li-Hsiang Shen 2022-12-20
9589971 Anti-fuse one-time programmable memory cell and anti-fuse one-time programmable memory array Chia-Chiuan Chang, Jui-Lung Chen, Yu-Wen Chen, Hsuan-Chi SU 2017-03-07
7580309 Memory refresh method and system Fan Yang, Jie Ding 2009-08-25
7540573 Cabinet with a safety device 2009-06-02
7309114 Cabinet with a safety device 2007-12-18
5404379 Timing recovery method and system Sammy Shyue, Ji-Shang Yu, Yen-Chun Lin 1995-04-04