Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6907520 | Threshold-based load address prediction and new thread identification in a multithreaded microprocessor | — | 2005-06-14 |
| 6859844 | Electro-optically connected multiprocessor configuration including a ring structured shift-register | — | 2005-02-22 |
| 6578137 | Branch and return on blocked load or store | — | 2003-06-10 |
| 6437653 | Method and apparatus for providing a variable inductor on a semiconductor chip | Jose M. Cruz | 2002-08-20 |
| 6408368 | Operating system page placement to maximize cache data reuse | — | 2002-06-18 |
| 6385657 | Chain transaction transfers between ring computer systems coupled by bridge modules | — | 2002-05-07 |
| 6295600 | Thread switch on blocked load or store using instruction thread field | — | 2001-09-25 |
| 6115756 | Electro-optically connected multiprocessor and multiring configuration for dynamically allocating time | — | 2000-09-05 |
| 6055613 | System and method for transferring data and status information between memories of different types occupying a single real address space using a dedicated memory transfer bus | — | 2000-04-25 |
| 6006320 | Processor architecture with independent OS resources | — | 1999-12-21 |
| 5933627 | Thread switch on blocked load or store using instruction thread field | — | 1999-08-03 |
| 5812816 | System and method for transferring data between memories of different types occupying a single real address space using a dedicated memory transfer bus | — | 1998-09-22 |
| 5649143 | Apparatus and method for providing a cache indexing scheme less susceptible to cache collisions | — | 1997-07-15 |