AC

Arindam Chatterjee

CS Cadence Design Systems: 16 patents #57 of 2,263Top 3%
WL Wipro Limited: 11 patents #24 of 690Top 4%
AE American Express: 10 patents #94 of 1,774Top 6%
Microsoft: 6 patents #7,383 of 40,388Top 20%
SY Synopsys: 3 patents #460 of 2,302Top 20%
EL Eli Lilly: 1 patents #1,742 of 2,858Top 65%
SU Saint Louis University: 1 patents #89 of 208Top 45%
📍 Saratoga, CA: #185 of 2,933 inventorsTop 7%
🗺 California: #8,490 of 386,348 inventorsTop 3%
Overall (All Time): #57,903 of 4,157,543Top 2%
48
Patents All Time

Issued Patents All Time

Showing 26–48 of 48 patents

Patent #TitleCo-InventorsDate
9166797 Secured compartment for transactions Thekkthalackal Varugis Kurien, Cormac Herley, Alice Jane Bernheim Brush, Daniel C. Robbins, Scott A. Field 2015-10-20
8661534 Security system with compliance checking and remediation Anders Samuelsson, Nils Dussart, Charles G. Jeffries, Amit Raghunath Kulkarni 2014-02-25
8533841 Deriving remediations from security compliance rules Amit Raghunath Kulkarni, Tristan A. Brown 2013-09-10
8332909 Automated software restriction policy rule generation Varugis Kurien, Bental Tagor, Sanjeev Dwivedi 2012-12-11
8161560 Extensible framework for system security state reporting and remediation Charles G. Jeffries, Doug Coburn, Barry Gerhardt, Randall K. Winjum 2012-04-17
7908659 Extensible framework for system security state reporting and remediation Charles G. Jeffries, Doug Coburn, Barry Gerhardt, Randall K. Winjum 2011-03-15
7511065 Mixed lineage kinase modulators Theodore Goodson, Jr., Mary Margaret Mader, John E. Toth, Jason Scott Sawyer 2009-03-31
7114138 Method and apparatus for extracting resistance from an integrated circuit design Steven Teig 2006-09-26
7103524 Method and apparatus for creating an extraction model using Bayesian inference implemented with the Hybrid Monte Carlo method Steven Teig 2006-09-05
7086021 Method and arrangement for extracting capacitance in integrated circuits having non manhattan wiring Steven Teig 2006-08-01
7051293 Method and apparatus for creating an extraction model Steven Teig 2006-05-23
6961914 Method and apparatus for selecting input points to train a machine learning model for extraction Steven Teig 2005-11-01
6941531 Method and apparatus for performing extraction on an integrated circuit design Steven Teig 2005-09-06
6925618 Method and apparatus for performing extraction on an integrated circuit design with support vector machines Steven Teig 2005-08-02
6907591 Method and apparatus for performing extraction using a neural network Steven Teig 2005-06-14
6892366 Method and apparatus for performing extraction using a model trained with Bayesian inference via a Monte Carlo method Steven Teig 2005-05-10
6883148 Method and apparatus for creating an extraction model using Bayesian inference Steven Teig 2005-04-19
6880138 Method and apparatus for creating a critical input space spanning set of input points to train a machine learning model for extraction Steven Teig 2005-04-12
6857112 Method and apparatus for performing extraction using machine learning Steven Teig 2005-02-15
6854101 Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring Steven Teig 2005-02-08
6735748 Method and apparatus for performing extraction using a model trained with bayesian inference Steven Teig 2004-05-11
6687887 Method and apparatus for performing extraction using a model trained with Bayesian inference using a hybrid monte carlo method Steven Teig 2004-02-03
6581198 Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring Steven Teig 2003-06-17