AT

Anurag Tomar

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 San Jose, CA: #17,604 of 32,062 inventorsTop 55%
🗺 California: #185,134 of 386,348 inventorsTop 50%
Overall (All Time): #2,000,008 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9262359 Method and system for implementing pipeline flip-flops David C. Noice, Scot A. Woodward, Adrian Aloysius Hendroff, Dennis Huang 2016-02-16
7802219 Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout Dave Noice 2010-09-21