Issued Patents All Time
Showing 226–241 of 241 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5257229 | Column redundancy architecture for a read/write memory | Narasimhan Iyengar | 1993-10-26 |
| 5257226 | Integrated circuit with self-biased differential data lines | — | 1993-10-26 |
| 5206817 | Pipelined circuitry for allowing the comparison of the relative difference between two asynchronous pointers and a programmable value | — | 1993-04-27 |
| 5161159 | Semiconductor memory with multiple clocking for test mode entry | Thomas A. Coker | 1992-11-03 |
| 5128897 | Semiconductor memory having improved latched repeaters for memory row line selection | — | 1992-07-07 |
| 5124951 | Semiconductor memory with sequenced latched row line repeaters | William C. Slemmer | 1992-06-23 |
| 5124584 | Address buffer circuit with transition-based latching | — | 1992-06-23 |
| 5121346 | Difference comparison between two asynchronous pointers and a programmable value | — | 1992-06-09 |
| 5121358 | Semiconductor memory with power-on reset controlled latched row line repeaters | William C. Slemmer | 1992-06-09 |
| 5115146 | Power-on reset circuit for controlling test mode entry | — | 1992-05-19 |
| 5099148 | Integrated circuit having multiple data outputs sharing a resistor network | James Brady | 1992-03-24 |
| 5072138 | Semiconductor memory with sequential clocked access codes for test mode entry | William C. Slemmer, Thomas A. Coker | 1991-12-10 |
| 5019724 | Noise tolerant input buffer | — | 1991-05-28 |
| 5005158 | Redundancy for serial memory | Mark A. Lysinger | 1991-04-02 |
| 4974241 | Counter employing exclusive NOR gate and latches in combination | Mark A. Lysinger | 1990-11-27 |
| 4935719 | Comparator circuitry | — | 1990-06-19 |