SK

Stephen W. Kiss

IN Intel: 5 patents #7,174 of 30,777Top 25%
📍 Banks, OR: #20 of 75 inventorsTop 30%
🗺 Oregon: #7,313 of 28,073 inventorsTop 30%
Overall (All Time): #1,037,396 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
6968402 System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order David R. Jackson, Miles F. Schwartz 2005-11-22
6893925 Layout to minimize gate orientation related skew effects Jeffrey W. Bates 2005-05-17
6633927 Device and method to minimize data latency and maximize data throughput using multiple data valid signals David R. Jackson, Miles F. Schwartz 2003-10-14
6601224 Layout to minimize gate orientation related skew effects Jeffrey W. Bates 2003-07-29
6151257 Apparatus for receiving/transmitting signals in an input/output pad buffer cell Smith E. Jeffrey, Timothy Kelly, Keith Self 2000-11-21