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Handling multiple delayed write transactions simultaneously through a bridge |
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2002-08-27 |
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Trigger points for performance optimization in bus-to-bus bridges |
Barry R. Davis |
2001-10-02 |
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Read latency across a bridge |
Bineet Thaker |
2001-07-10 |
| 6230228 |
Efficient bridge architecture for handling multiple write transactions simultaneously |
Bryan R. White |
2001-05-08 |
| 6067629 |
Apparatus and method for pseudo-synchronous communication between clocks of different frequencies |
Joseph Murray, Jeff J. McCoskey |
2000-05-23 |
| 5884027 |
Architecture for an I/O processor that integrates a PCI to PCI bridge |
Elliot Garbus, Peter Sankhagowit, Marc A. Goldschmidt |
1999-03-16 |
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Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port |
David Sprague |
1998-10-27 |
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Method and apparatus for asynchronous, bi-directional communication between first and second logic elements having a fixed priority arbitrator |
— |
1996-05-07 |