Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12210477 | Systems and methods for improving cache efficiency and utilization | Altug Koker, Joydeep Ray, Ben J. Ashbaugh, Jonathan Pearce, Abhishek R. Appu +19 more | 2025-01-28 |
| 11907146 | Systems and methods for intelligently implementing concurrent transfers of data within a machine perception and dense algorithm integrated circuit | Aman Sikka, Nigel Drego, Veerbhan Kheterpal | 2024-02-20 |
| 11714556 | Systems and methods for accelerating memory transfers and computation efficiency using a computation-informed partitioning of an on-chip data buffer and implementing computation-aware data transfer operations to the on-chip data buffer | Aman Sikka, Nigel Drego, Veerbhan Kheterpal, Daniel Firu, Mrinalini Ravichandran | 2023-08-01 |
| 11709714 | Thread group scheduling for graphics processing | Ben J. Ashbaugh, Jonathan Pearce, Murali Ramadoss, Vikranth Vemulapalli, William Sadler +1 more | 2023-07-25 |
| 11620256 | Systems and methods for improving cache efficiency and utilization | Altug Koker, Joydeep Ray, Ben J. Ashbaugh, Jonathan Pearce, Abhishek R. Appu +19 more | 2023-04-04 |
| 11531633 | Systems and methods for intelligently implementing concurrent transfers of data within a machine perception and dense algorithm integrated circuit | Aman Sikka, Nigel Drego, Veerbhan Kheterpal | 2022-12-20 |
| 11416411 | Preemptive page fault handling | Murali Ramadoss, Vikranth Vemulapalli, Niran Cooray, William Sadler, Jonathan Pearce +9 more | 2022-08-16 |
| 11281496 | Thread group scheduling for graphics processing | Ben J. Ashbaugh, Jonathan Pearce, Murali Ramadoss, Vikranth Vemulapalli, William Sadler +1 more | 2022-03-22 |
| 5083787 | Combinational logic system | — | 1992-01-28 |