Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10182236 | Field programmable object array having image processing circuitry | Richard D. Reohr, Jr. | 2019-01-15 |
| 10021407 | Field programmable object array having image processing circuitry | Richard D. Reohr, Jr. | 2018-07-10 |
| 9648345 | Field programmable object array having image processing circuitry | Richard D. Reohr, Jr. | 2017-05-09 |
| 9419620 | Field programmable object array and video compression processor for video data compression | Richard D. Reohr, Jr. | 2016-08-16 |
| 7689853 | Synchronization of network communication link | — | 2010-03-30 |
| 7570659 | Multi-lane receiver de-skewing | Richard D. Reohr, Jr. | 2009-08-04 |
| 7450583 | Device to receive, buffer, and transmit packets of data in a packet switching network | Tom E. Burton, Dominic J. Gasbarro, Brian M. Leitner | 2008-11-11 |
| 7352763 | Device to receive, buffer, and transmit packets of data in a packet switching network | Tom E. Burton, Dominic J. Gasbarro, Brian M. Leitner | 2008-04-01 |
| 7190667 | Link level packet flow control mechanism | Richard D. Reohr, Jr. | 2007-03-13 |
| 7054331 | Multi-lane receiver de-skewing | Richard D. Reohr, Jr. | 2006-05-30 |
| 7003059 | Jabber counter mechanism for elastic buffer operation | Richard D. Reohr, Jr. | 2006-02-21 |
| 6778548 | Device to receive, buffer, and transmit packets of data in a packet switching network | Tom E. Burton, Dominic J. Gasbarro, Brian M. Leitner | 2004-08-17 |
| 6751235 | Communication link synchronization method | Richard D. Reohr, Jr. | 2004-06-15 |
| 6747997 | Network channel receiver architecture | Richard D. Reohr, Jr. | 2004-06-08 |
| 6745353 | Method and apparatus for sliding window link physical error detection | Richard D. Reohr, Jr., Timothy Barilovits | 2004-06-01 |
| 6741602 | Work queue alias system and method allowing fabric management packets on all ports of a cluster adapter | Richard D. Reohr, Jr. | 2004-05-25 |
| 6725388 | Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains | — | 2004-04-20 |
| 6625768 | Test bus architecture | Richard D. Reohr, Jr., Brian M. Collins, Tom E. Burton, Dominic J. Gasbarro, Brian M. Leitner +1 more | 2003-09-23 |
| 6606328 | Look ahead encoder/decoder architecture | — | 2003-08-12 |
| 6594329 | Elastic buffer | — | 2003-07-15 |
| 6438728 | Error character generation | — | 2002-08-20 |