Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10754413 | Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode | Vasudev Bibikar, Chin Seng Lu, Moorthy Rajesh, Darren Crews | 2020-08-25 |
| 10261572 | Technologies for managing power during an activation cycle | Arvind Raman | 2019-04-16 |
| 9625984 | Technologies for managing power during an activation cycle | Arvind Raman | 2017-04-18 |