Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8912834 | Integrated circuits with dual-edge clocking | David Lewis | 2014-12-16 |
| 8519763 | Integrated circuits with dual-edge clocking | David Lewis | 2013-08-27 |
| 8205178 | Common clock path pessimism analysis for circuit designs using clock tree networks | — | 2012-06-19 |
| 8028260 | Determination of most critical timing paths in digital circuits | — | 2011-09-27 |
| 7926019 | Common clock path pessimism analysis for circuit designs using clock tree networks | — | 2011-04-12 |
| 7424692 | Methods to find worst-case setup and hold relationship for static timing analysis | — | 2008-09-09 |