Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12408364 | Hole draining structure for suppression of hole accumulation | Hyeongnam Kim | 2025-09-02 |
| 12349389 | Lateral III/V heterostructure field effect transistor | Hyeongnam Kim | 2025-07-01 |
| 12040302 | Device package having a lateral power transistor with segmented chip pad | Hyeongnam Kim | 2024-07-16 |
| 11923448 | High voltage blocking III-V semiconductor device | Hyeongnam Kim, Jens Ulrich Heinle, Bhargav Pandya, Ramakrishna Tadikonda, Manuel Vorwerk | 2024-03-05 |
| 11916068 | Type III-V semiconductor substrate with monolithically integrated capacitor | Hyeongnam Kim | 2024-02-27 |
| 11862630 | Semiconductor device having a bidirectional switch and discharge circuit | Hyeongnam Kim, Kennith Kin Leong, Bhargav Pandya, Gerhard Prechtl | 2024-01-02 |
| 11588024 | High voltage blocking III-V semiconductor device | Shu Yang, Giorgia Longobardi, Florin Udrea, Dario Pagnano, Gianluca Camuso +2 more | 2023-02-21 |
| 11575377 | Switching circuit, gate driver and method of operating a transistor device | Hyeongnam Kim, Alain Charles, Qin Lei, Chunhui Liu | 2023-02-07 |
| 11545485 | Type III-V semiconductor substrate with monolithically integrated capacitor | Hyeongnam Kim | 2023-01-03 |
| 11251294 | High voltage blocking III-V semiconductor device | Hyeongnam Kim, Jens Ulrich Heinle, Bhargav Pandya, Ramakrishna Tadikonda, Manuel Vorwerk | 2022-02-15 |
| 10211329 | Charge trapping prevention III-Nitride transistor | Hyeongnam Kim, Alain Charles, Jianwei Wan, Mihir Tungare, Chan Kyung Choi | 2019-02-19 |
| 9461034 | Composite group III-V and group IV transistor having a switched substrate | Yang Pan | 2016-10-04 |
| 9397089 | Group III-V HEMT having a selectably floating substrate | Yang Pan | 2016-07-19 |
| 7208385 | LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance | Zia Hossain, Joe Fulton | 2007-04-24 |
| 6919598 | LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance | Zia Hossain, Joe Fulton | 2005-07-19 |
| 6867083 | Method of forming a body contact of a transistor and structure therefor | Jefferson W. Hall | 2005-03-15 |
| 6773997 | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability | Joe Fulton, Zia Hossain, Masami Tanaka, Taku Yamamoto, Yoshio Enosawa +2 more | 2004-08-10 |
| 6589845 | Method of forming a semiconductor device and structure therefor | Rajesh S. Nair, Zia Hossain, Takeshi Ishiguro | 2003-07-08 |
| 6555877 | NMOSFET with negative voltage capability formed in P-type substrate and method of making the same | Raj Nair, Mohammed Tanvir Quddus, Masaru Suzuki, Takeshi Ishiguro, Jefferson W. Hall | 2003-04-29 |
| 6507058 | Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same | Jefferson W. Hall, Zia Hossain, Mohammed Tanvir Quddus, Joe Fulton | 2003-01-14 |
| 6492679 | Method for manufacturing a high voltage MOSFET device with reduced on-resistance | Joe Fulton, Zia Hossain, Masami Tanaka, Taku Yamamoto, Yoshio Enosawa +2 more | 2002-12-10 |
| 6492687 | Merged semiconductor device and method | Raj Nair, Charles Hoggatt | 2002-12-10 |
| 6448625 | High voltage metal oxide device with enhanced well region | Zia Hossain, Evgueniy Stefanov, Mohammed Tanvir Quddus, Joe Fulton | 2002-09-10 |
| 6262468 | Inductor formed at least partially in a substrate | Sittampalam Yoganathan | 2001-07-17 |
| 6111451 | Efficient VCCP supply with regulation for voltage control | Patrick J. Mullarkey | 2000-08-29 |