Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8854866 | Identification circuit and method for generating an identification bit | Peter Huber, Winfried Kamp, Joel Hatsch, Michel d'Argouges, Thomas Kuenemund | 2014-10-07 |
| 8780648 | Latch based memory device | Winfried Kamp, Julie Aunis | 2014-07-15 |
| 8605526 | Memory reliability verification techniques | Peter Huber, Joel Hatsch, Karl Hofmann | 2013-12-10 |
| 8331163 | Latch based memory device | Winfried Kamp, Julie Aunis | 2012-12-11 |
| 8243555 | Apparatus and system with a time delay path and method for propagating a timing event | Stephan Henzler | 2012-08-14 |
| 8223573 | Method and device for controlling a memory access and correspondingly configured semiconductor memory | Martin Ostermayr | 2012-07-17 |
| 8209523 | Data moving processor | Ulf Nordqvist, Jinan Lin, Xiaoning Nie, Stefan Maier | 2012-06-26 |
| 7656204 | Divider circuit | Stephan Henzler | 2010-02-02 |
| 7492187 | Circuit arrangement for supplying configuration data in FPGA devices | Winfried Kamp, Michael Scheppler | 2009-02-17 |
| 7439765 | Mask-programmable logic macro and method for programming a logic macro | Winfried Kamp, Michael Scheppler | 2008-10-21 |
| 7177385 | Shift register for safely providing a configuration bit | Georg Georgakos, Thomas Niedermeier | 2007-02-13 |
| 5610531 | Testing method for semiconductor circuit levels | Werner Weber, Helmut Klose, Holger Huebner | 1997-03-11 |
| 4868825 | Method for simulating an open fault in a logic circuit comprising field effect transistors and simulation models for implementing the method | — | 1989-09-19 |
| 4852093 | Method for simulating a fault in a logic circuit and a simulation model for the implementation of the method | — | 1989-07-25 |
| 4799096 | Monolithic integrated circuit comprising circuit branches parallel to one another | — | 1989-01-17 |