Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12190224 | Processing elements array that includes delay queues between processing elements to hold shared data | Yao-Hua Chen, Yu-Xiang Yen, Wan-Shan HSIEH, Juin-Ming Lu, Jing-Jia Liou | 2025-01-07 |
| 11657273 | Hardware structure aware adaptive learning based power modeling method and system | Yao-Hua Chen, Jing-Jia Liou, Juin-Ming Lu | 2023-05-23 |
| 11551066 | Deep neural networks (DNN) hardware accelerator and operation method thereof | Yao-Hua Chen, Chun-Chen Chen, Jing-Jia Liou, Chun-Hung Lai, Juin-Ming Lu | 2023-01-10 |
| 10365829 | Memory transaction-level modeling method and system | Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou | 2019-07-30 |
| 7904768 | Probing system for integrated circuit devices | Cheng-Wen Wu, Yu-Tsao Hsing | 2011-03-08 |
| 7861070 | Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized | Yen-Ju Ho, Ming-Chang Hsieh | 2010-12-28 |
| 7675309 | Probing system for integrated circuit device | Cheng-Wen Wu, Yu-Tsao Hsing | 2010-03-09 |
| 7117409 | Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction | Cheng-Wen Wu, Chih-Wea Wang, Kao-Liang Cheng | 2006-10-03 |
| 7065689 | Diagonal testing method for flash memories | Sau-Kwo Chiu, Jen-Chieh Yeh, Kuo-Liang Cheng, Cheng-Wen Wu | 2006-06-20 |
| 6934900 | Test pattern generator for SRAM and DRAM | Chuang-Yuan Cheng, Jing-Reng Huang, Cheng-Wen Wu | 2005-08-23 |
| 6415403 | Programmable built in self test for embedded DRAM | Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu | 2002-07-02 |