Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10949277 | Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit | Matthew G. Borlick, Lokesh M. Gupta | 2021-03-16 |
| 10936369 | Maintenance of local and global lists of task control blocks in a processor-specific manner for allocation to tasks | Sean P. Riley | 2021-03-02 |
| 10831559 | Processor thread management | Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta | 2020-11-10 |
| 10810304 | Injecting trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code | Lokesh M. Gupta, Matthew G. Borlick, Micah Robison | 2020-10-20 |
| 10740030 | Stopping a plurality of central processing units for data collection based on attributes of tasks | Louis A. Rasor, Juan J. Ruiz | 2020-08-11 |
| 10733025 | Balancing categorized task queues in a plurality of processing entities of a computational device | Seamus J. Burke, Louis A. Rasor | 2020-08-04 |
| 10691502 | Task queuing and dispatching mechanisms in a computational device | Seamus J. Burke, Louis A. Rasor | 2020-06-23 |
| 10671438 | Providing additional memory and cache for the execution of critical tasks by folding processing units of a processor complex | Matthew G. Borlick, Lokesh M. Gupta | 2020-06-02 |
| 10642755 | Invoking demote threads on processors to demote tracks from a cache based on free cache segments | Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta | 2020-05-05 |
| 10606714 | Stopping central processing units for data collection based on event categories of events | Matthew D. Carson, Louis A. Rasor, Todd C. Sorenson | 2020-03-31 |
| 10579413 | Efficient task scheduling using a locking mechanism | Michael T. Benhase, Lokesh M. Gupta, David B. Whitworth | 2020-03-03 |
| 10565020 | Adjustment of the number of central processing units to meet performance requirements of an I/O resource | Veronica S. Davila, Louis A. Rasor | 2020-02-18 |
| 10545795 | Determination of memory access patterns of tasks in a multi-core processor | Matthew G. Borlick, Lokesh M. Gupta | 2020-01-28 |
| 10540170 | Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment | Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch +3 more | 2020-01-21 |
| 10528437 | Monitoring correctable errors on a bus interface to determine whether to redirect input/output request (I/O) traffic to another bus interface | Matthew G. Borlick, Lokesh M. Gupta | 2020-01-07 |
| 10528412 | Multiple path error data collection in a storage management system | Gary W. Batchelor, Matthew D. Carson, Enrique Q. Garcia, Larry Juarez, Jay T. Kirch +3 more | 2020-01-07 |
| 10430264 | Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit | Matthew G. Borlick, Lokesh M. Gupta | 2019-10-01 |
| 10394713 | Selecting resources to make available in local queues for processors to use | Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta | 2019-08-27 |
| 10387218 | Lock profiling tool to identify code bottlenecks in a storage controller | Louis A. Rasor | 2019-08-20 |
| 10379943 | Management of foreground and background processes in a storage controller | Matthew G. Borlick, Lokesh M. Gupta, Karl A. Nielsen | 2019-08-13 |
| 10346317 | Determining cores to assign to cache hostile tasks | Matthew G. Borlick, Lokesh M. Gupta | 2019-07-09 |
| 10318156 | Invoking input/output (I/O) threads on processors to demote tracks from a cache | Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta | 2019-06-11 |
| 10275280 | Reserving a core of a processor complex for a critical task | Matthew G. Borlick, Lokesh M. Gupta, Clint A. Hardy | 2019-04-30 |
| 10255223 | Detecting a type of storage adapter connected and miscabling of a microbay housing the storage adapter | Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Todd C. Sorenson | 2019-04-09 |
| 10248464 | Providing additional memory and cache for the execution of critical tasks by folding processing units of a processor complex | Matthew G. Borlick, Lokesh M. Gupta | 2019-04-02 |