Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8161445 | Logic transformation and gate placement to avoid routing congestion | Chaitra Bhat, Chandrika Madhwacharya, Atsushi Sugai | 2012-04-17 |
| 8006210 | Logic transformation and gate placement to avoid routing congestion | Chaitra Bhat, Chandrika Madhwacharya, Atsushi Sugai | 2011-08-23 |
| 7930608 | Circuit for controlling voltage fluctuation in integrated circuit | — | 2011-04-19 |
| 7793183 | Microcomputer and method of testing the same | Ken Namura, Mitsuru Sugimoto | 2010-09-07 |
| 7752513 | Method and circuit for LSSD testing | Ken Namura, Sanae Seike | 2010-07-06 |
| 7752586 | Design structure of an integration circuit and test method of the integrated circuit | — | 2010-07-06 |
| 7356797 | Logic transformation and gate placement to avoid routing congestion | Chaitra Bhat, M. Chandrika, Atsushi Sugai | 2008-04-08 |