Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9223728 | Servicing a globally broadcast interrupt signal in a multi-threaded computer | John E. Attinella, Kristan D. Davis, David L. Satterfield | 2015-12-29 |
| 9223729 | Servicing a globally broadcast interrupt signal in a multi-threaded computer | John E. Attinella, Kristan D. Davis, David L. Satterfield | 2015-12-29 |
| 8874722 | Interactive tool for visualizing performance data in real-time to enable adaptive performance optimization and feedback | Thomas M. Gooding, David L. Hermsmeier, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz | 2014-10-28 |
| 8443287 | Interactive tool for visualizing performance data in real-time to enable adaptive performance optimization and feedback | Thomas M. Gooding, David L. Hermsmeier, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz | 2013-05-14 |
| 8031614 | Method and apparatus for routing data in an inter-nodal communications lattice of a massively parallel computer system by dynamic global mapping of contended links | Charles J. Archer, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz, Brian Paul Wallenfelt | 2011-10-04 |
| 7839786 | Method and apparatus for routing data in an inter-nodal communications lattice of a massively parallel computer system by semi-randomly varying routing policies for different packets | Charles J. Archer, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz, Brian Paul Wallenfelt | 2010-11-23 |
| 7835284 | Method and apparatus for routing data in an inter-nodal communications lattice of a massively parallel computer system by routing through transporter nodes | Charles J. Archer, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz, Brian Paul Wallenfelt | 2010-11-16 |
| 7716036 | Method and apparatus to use clock bursting to minimize command latency in a logic simulation hardware emulator / accelerator | — | 2010-05-11 |
| 7706275 | Method and apparatus for routing data in an inter-nodal communications lattice of a massively parallel computer system by employing bandwidth shells at areas of overutilization | Charles J. Archer, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz, Brian Paul Wallenfelt | 2010-04-27 |
| 7680048 | Method and apparatus for routing data in an inter-nodal communications lattice of a massively parallel computer system by dynamically adjusting local routing strategies | Charles J. Archer, Amanda Peters, Kurt Walter Pinnow, Brent Allen Swartz, Brian Paul Wallenfelt | 2010-03-16 |
| 7480611 | Method and apparatus to increase the usable memory capacity of a logic simulation hardware emulator/accelerator | Thomas M. Gooding | 2009-01-20 |
| 7437282 | Method and apparatus to provide alternative stimulus to signals internal to a model actively running on a logic simulation hardware emulator | — | 2008-10-14 |
| 7337103 | Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator | Thomas M. Gooding | 2008-02-26 |
| 6842728 | Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments | Thomas M. Gooding, Robert Neill Newshutz, Jeffrey Joseph Ruedinger | 2005-01-11 |
| 6832185 | Non-synchronous hardware emulator | Jeffrey Joseph Ruedinger | 2004-12-14 |
| 6556936 | Method and apparatus for correlating trace data from asynchronous emulation machines | Thomas M. Gooding, Robert Neill Newshutz, Jeffery Joseph Ruedinger | 2003-04-29 |
| 6035117 | Tightly coupled emulation processors | William F. Beausoleil, Tak-kwong Ng, Helmut Roth | 2000-03-07 |
| 5946472 | Apparatus and method for performing behavioral modeling in hardware emulation and simulation environments | Jeffrey Steven Graves, Jeffrey Joseph Ruedinger | 1999-08-31 |