Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8132178 | System and method for delayed priority boost | Jos Manuel Accapadi, Andrew Dunshea, Dirk Michel | 2012-03-06 |
| 8010948 | System and method for measuring latch contention | David Mehaffy | 2011-08-30 |
| 7620661 | Method for improving the performance of database loggers using agent coordination | David Mehaffy | 2009-11-17 |
| 7448036 | System and method for thread scheduling with weak preemption policy | Larry Bert Brenner, Mysore S. Srinivas | 2008-11-04 |
| 7380247 | System for delaying priority boost in a priority offset amount only after detecting of preemption event during access to critical section | Jos Manuel Accapadi, Andrew Dunshea, Dirk Michel | 2008-05-27 |
| 7318220 | System and method for measuring latch contention | David Mehaffy | 2008-01-08 |
| 7278141 | System and method for adding priority change value corresponding with a lock to a thread during lock processing | Jos Manuel Accapadi, Andrew Dunshea, Dirk Michel | 2007-10-02 |
| 6910212 | System and method for improved complex storage locks | Larry Bert Brenner, Bimal Kiran Doshi, Greg R. Mewhinney | 2005-06-21 |
| 6336170 | Method and system in a distributed shared-memory data processing system for determining utilization of shared-memory included within nodes by a designated application | Mark E. Dean, James M. Magee, Ronald L. Rockhold, Guy G. Sotomayor | 2002-01-01 |
| 5961583 | Method and system for using the event wait list anchor as a lock for events | — | 1999-10-05 |
| 5963737 | Interupt vectoring for trace exception facility in computer systems | Bruce G. Mealey, Michael Stephen Williams | 1999-10-05 |
| 5873116 | Method and apparatus for controlling access to data structures without the use of locks | — | 1999-02-16 |
| 5790846 | Interrupt vectoring for instruction address breakpoint facility in computer systems | Bruce G. Mealey, Michael Stephen Williams | 1998-08-04 |
| 5764884 | Method and apparatus for improved instruction counting schemes | — | 1998-06-09 |
| 5758168 | Interrupt vectoring for optionally architected facilities in computer systems | Bruce G. Mealey, Michael Stephen Williams | 1998-05-26 |