Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8994460 | Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications | James D. Strom, Kenneth A. Van Goor, Kennedy K. Cheruiyot | 2015-03-31 |
| 8917126 | Charge pump operating voltage range control using dynamic biasing | Joel T. Ficke, David M. Friend, James D. Strom | 2014-12-23 |
| 8751982 | Implementing dual speed level shifter with automatic mode control | Joel T. Ficke, David M. Friend, James D. Strom, Jianguo Yao | 2014-06-10 |
| 8686782 | Structure for a frequency adaptive level shifter circuit | Joel T. Ficke, David M. Friend, James D. Strom, Jianguo Yao | 2014-04-01 |
| 8547154 | Programmable duty cycle selection using incremental pulse widths | Pradeep Thiagarajan | 2013-10-01 |
| 8513957 | Implementing integral dynamic voltage sensing and trigger | Kennedy K. Cheruiyot, Joel T. Ficke, David M. Friend, James D. Strom | 2013-08-20 |
| 8415969 | Implementing screening for single FET compare of physically unclonable function (PUF) | Joel T. Ficke, James D. Strom | 2013-04-09 |
| 8373486 | Structure for a frequency adaptive level shifter circuit | Joel T. Ficke, David M. Friend, James D. Strom, Jianguo Yao | 2013-02-12 |
| 8324933 | Implementing dual speed level shifter with automatic mode control | Joel T. Ficke, David M. Friend, James D. Strom, Jianguo Yao | 2012-12-04 |
| 8237510 | Implementing phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock | Joel T. Ficke, James D. Strom | 2012-08-07 |
| 7532040 | Programmable sensitivity frequency coincidence detection circuit and method | Ram Kelkar | 2009-05-12 |
| 7477075 | CMOS output driver using floating wells to prevent leakage current | — | 2009-01-13 |