Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8166357 | Implementing logic security feature for disabling integrated circuit test ports ability to scanout data | Dennis Martin Rickert, Brian Andrew Schuelke | 2012-04-24 |
| 7724022 | Implementing enhanced security features in an ASIC using eFuses | Brian P. Deskin, William E. Hall | 2010-05-25 |
| 6658616 | Method for improving the efficiency of weighted random pattern tests through reverse weight simulation using effective pattern masks | Paul Chang | 2003-12-02 |