Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10659348 | Holding of a link in an optical interface by a lower level processor until authorization is received from an upper level processor | Mark P. Bendyk, Roger G. Hathorn, Steven E. Klein | 2020-05-19 |
| 10606780 | Programming interface operations in a driver in communication with a port for reinitialization of storage controller elements | Roger G. Hathorn, Steven E. Klein, Bernhard Laubli | 2020-03-31 |
| 10579579 | Programming interface operations in a port in communication with a driver for reinitialization of storage controller elements | Roger G. Hathorn, Steven E. Klein, Bernhard Laubli | 2020-03-03 |
| 10331568 | Locking a cache line for write operations on a bus | Stephen L. Blinick, Roger G. Hathorn, Benhard Laubli, Miguel A. Montoya, Timothy J. Van Patten | 2019-06-25 |
| 10083144 | Programming interface operations in a port in communication with a driver for reinitialization of storage controller elements | Roger G. Hathorn, Steven E. Klein, Bernhard Laubli | 2018-09-25 |
| 10049050 | Locking a cache line for write operations on a bus | Stephen L. Blinick, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten | 2018-08-14 |
| 9942134 | Holding of a link in an optical interface by a lower level processor until authorization is received from an upper level processor | Mark P. Bendyk, Roger G. Hathorn, Steven E. Klein | 2018-04-10 |
| 9928196 | Programming interface operations in a driver in communication with a port for reinitialization of storage controller elements | Roger G. Hathorn, Steven E. Klein, Bernhard Laubli | 2018-03-27 |
| 9811336 | Determining processor offsets to synchronize processor time values | Bernhard Laubli, Timothy J. Van Patten | 2017-11-07 |
| 9436607 | Locking a cache line for write operations on a bus | Stephen L. Blinick, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten | 2016-09-06 |
| 9075720 | Locking a cache line for write operations on a bus | Stephen L. Blinick, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten | 2015-07-07 |
| 8935511 | Determining processor offsets to synchronize processor time values | Bernhard Laubli, Timothy J. Van Patten | 2015-01-13 |
| 8904058 | Selecting direct memory access engines in an adaptor input/output (I/O) requests received at the adaptor | Roger G. Hathorn, Matthew J. Kalos, Timothy J. Van Patten | 2014-12-02 |
| 8850262 | Inter-processor failure detection and recovery | Roger G. Hathorn, Bernhard Laubli, Timothy J. Van Patten | 2014-09-30 |
| 8769173 | Systems and methods for detecting supported small form-factor pluggable (SFP) devices | Roger G. Hathorn, Steven E. Klein, Ashwani Kumar, Daniel W. Sherman | 2014-07-01 |
| 8606973 | Managing monitored conditions in adaptors in a multi-adaptor system | Steven E. Klein, Ashwani Kumar, John Norbert McCauley, Todd C. Sorenson | 2013-12-10 |
| 7523450 | Apparatus, system, and method for identifying fixed memory address errors in source code at build time | — | 2009-04-21 |
| 7475291 | Apparatus and method to generate and save run time data | Roger G. Hathorn, Man Wah Ma, Kimberly Thomas | 2009-01-06 |
| 7340595 | Multiplex execution-path system | Stephen L. Blinick, Ricardo Padilla | 2008-03-04 |
| 7337367 | Management of memory controller reset | Lucien Mirabeau, Man Wah Ma, Ricardo Padilla | 2008-02-26 |