Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering | William M. Clark, Jr., Lap-Wai Chow | 2007-01-23 |
| 7049667 | Conductive channel pseudo block process and circuit to inhibit reverse engineering | Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison | 2006-05-23 |
| 7008873 | Integrated circuit with reverse engineering protection | Lap-Wai Chow, William M. Clark, Jr. | 2006-03-07 |
| 6979606 | Use of silicon block process step to camouflage a false transistor | Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison | 2005-12-27 |
| 6940764 | Memory with a bit line block and/or a word line block for preventing reverse engineering | William M. Clark, Jr., Lap-Wai Chow | 2005-09-06 |
| 6924552 | Multilayered integrated circuit with extraneous conductive traces | Lap-Wai Chow, William M. Clark, Jr., Paul Ou Yang | 2005-08-02 |
| 6919600 | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact | Lap-Wai Chow, William M. Clark, Jr. | 2005-07-19 |
| 6897535 | Integrated circuit with reverse engineering protection | Lap-Wai Chow, William M. Clark, Jr. | 2005-05-24 |
| 6893916 | Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same | Lap-Wai Chow, William M. Clark, Jr. | 2005-05-17 |
| 6815816 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering | William M. Clark, Jr., Lap-Wai Chow | 2004-11-09 |
| 6791191 | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations | Lap-Wai Chow, William M. Clark, Jr. | 2004-09-14 |
| 6774413 | Integrated circuit structure with programmable connector/isolator | Lap-Wai Chow, William M. Clark, Jr. | 2004-08-10 |
| 6740942 | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact | Lap-Wai Chow, William M. Clark, Jr. | 2004-05-25 |
| 6613661 | Process for fabricating secure integrated circuit | William M. Clark, Jr., Lap-Wai Chow, Allan R. Kramer | 2003-09-02 |
| 6459629 | Memory with a bit line block and/or a word line block for preventing reverse engineering | William M. Clark, Jr., Lap-Wai Chow | 2002-10-01 |
| 6294816 | Secure integrated circuit | William M. Clark, Jr., Lap-Wai Chow, Allan R. Kramer | 2001-09-25 |
| 6117762 | Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering | Lap-Wai Chow, William M. Clark, Jr. | 2000-09-12 |
| 6064110 | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering | Lap-Wai Chow, William M. Clark, Jr. | 2000-05-16 |
| 5973375 | Camouflaged circuit structure with step implants | Lap-Wai Chow, William M. Clark, Jr. | 1999-10-26 |
| 5930663 | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering | Lap-Wai Chow, William M. Clark, Jr. | 1999-07-27 |
| 5866933 | Integrated circuit security system and method with implanted interconnections | William M. Clark, Jr., Lap-Wai Chow, Allan R. Kramer | 1999-02-02 |
| 5783846 | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering | Lap-Wai Chow, William M. Clark, Jr. | 1998-07-21 |
| 5357572 | Apparatus and method for sensitive circuit protection with set-scan testing | Mark E. Bianco, Douglas Dwyer, David J. Knobbe, Allan R. Kramer, Faik S. Ozdemir | 1994-10-18 |
| 5188671 | Multichannel plate assembly for gas source molecular beam epitaxy | Jennifer J. Zinck | 1993-02-23 |