Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6980385 | Apparatus for information recording and reproducing | Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai +2 more | 2005-12-27 |
| 6791776 | Apparatus for information recording and reproducing | Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai +2 more | 2004-09-14 |
| 6700721 | Magnetic recording and reproducing apparatus and semiconductor integrated circuit for use in the same comprising a read/write signal processor having an interleave write data generator | Eisaku Saiki, Terumi Takashi, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Shoichi Miyazawa +1 more | 2004-03-02 |
| 6452736 | Magnetic recording and reproducing apparatus and a read/write amplifier having a signal transmission system with high speed of data write signal | Eisaku Saiki, Terumi Takashi, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Shoichi Miyazawa +1 more | 2002-09-17 |
| 5937020 | Digital information signal reproducing circuit and digital information system | Kenichi Hase, Ryutaro Horita, Tsuguyoshi Hirooka, Haruto Katsu, Takashi Nara +1 more | 1999-08-10 |
| 5872666 | Decoder circuitry with PRML signal processing for reproducing apparatus | Eisaku Saiki, Kazutosi Ashikawa, Seiichi Mita, Shoichi Miyazawa, Tsuguyoshi Hirooka | 1999-02-16 |
| 5867333 | Data recording and reproducing apparatus and phase locked loop circuit for use therein including D/A converters acting as charge pumps and a reference voltage source | Eisaku Saiki, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Seiichi Mita | 1999-02-02 |
| 5677802 | Phase locked loop circuit with adjustable offset characteristic, method for adjustment and apparatus | Eisaku Saiki, Masashi Mori, Shoichi Miyazawa, Terumi Takashi | 1997-10-14 |
| 5157354 | Phase-locked loop IC having ECL buffers | Eisaku Saiki, Fukashi Ohi, Akira Uragami, Tsuyoshi Tateyama | 1992-10-20 |