Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11499138 | Method for manufacturing peripheral nerve cells | Susumu Rokudai, Shinji Yoshiyama, Hiroyuki Takahashi | 2022-11-15 |
| 9107918 | Method for determining sensitivity to irinotecan and use thereof | Keiko Hiyama, Keiji Tanimoto | 2015-08-18 |
| 8980557 | Marker for determination of sensitivity to triplet combination anti-cancer agent | Hidetaka Eguchi, Satoru Wada | 2015-03-17 |
| 8952576 | Semiconductor device | Daisuke Sasaki, Masatoshi Hasegawa, Testuya Fukuoka | 2015-02-10 |
| 8638593 | Semiconductor device | Takumi Takagi, Daisuke Sasaki, Masatoshi Hasegawa | 2014-01-28 |
| 7596010 | Semiconductor memory device | Keiichi Higeta, Takashi Koba | 2009-09-29 |
| 7428682 | Semiconductor memory device | Yoichiro Aihara, Daisuke Sasaki | 2008-09-23 |
| 7349231 | Semiconductor memory device | Keiichi Higeta, Takashi Koba | 2008-03-25 |
| 7320482 | Semiconductor integrated circuit device | Hiroshi Toyoshima | 2008-01-22 |
| 7208924 | Semiconductor integrated circuit device | Hiroshi Toyoshima | 2007-04-24 |
| 7203081 | Semiconductor memory device | Keiichi Higeta, Takashi Koba | 2007-04-10 |
| 6909653 | Memory integrated circuit device having self reset circuit for precharging data buses based on the detection of their discharge levels | Daisuke Shimadu, Hiroshi Toyoshima | 2005-06-21 |
| 6865705 | Semiconductor integrated circuit device capable of switching mode for trimming internal circuitry through JTAG boundary scan method | Masahiko Tomizawa | 2005-03-08 |
| 6725325 | Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function | Kinya Mitsumoto, Takeshi Agari | 2004-04-20 |