Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7397104 | Semiconductor integrated circuit device and a method of manufacturing the same | Norio Suzuki, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe +6 more | 2008-07-08 |
| 7208391 | Method of manufacturing a semiconductor integrated circuit device that includes forming an isolation trench around active regions and filling the trench with two insulating films | Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa +1 more | 2007-04-24 |
| 7074691 | Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material | Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa +1 more | 2006-07-11 |
| 7060589 | Method for manufacturing a semiconductor integrated circuit device that includes covering the bottom of an isolation trench with spin-on glass and etching back the spin-on glass to a predetermined depth | Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa +1 more | 2006-06-13 |
| 6720234 | Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing | Norio Suzuki, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe +6 more | 2004-04-13 |
| 6693008 | Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device | Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa +1 more | 2004-02-17 |
| 6562695 | Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing | Norio Suzuki, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe +6 more | 2003-05-13 |