Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6823300 | Memory efficient occurrence model design for VLSI CAD | Richard Ferreri | 2004-11-23 |
| 6801884 | Method and apparatus for traversing net connectivity through design hierarchy | Richard Ferreri | 2004-10-05 |
| 6625798 | Method for translating conditional expressions from a non-verilog hardware description language to verilog hardware description language while preserving structure suitable for logic synthesis | Richard Ferreri | 2003-09-23 |
| 6564354 | Method for translating conditional expressions from a non-verilog hardware description language to verilog hardware description language while preserving structure suitable for logic synthesis | Paul Donald Hylander | 2003-05-13 |
| 6119079 | Method and structure for tokenized message logging system | Charles W. Cairns, Jr. | 2000-09-12 |