Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8862770 | Processor architecture verification | Zachary Smith | 2014-10-14 |
| 8693661 | Apparatus and methods for protection from inappropriate phone-dialing | Lisa F. Maly | 2014-04-08 |
| 7818646 | Expectation based event verification | Ryan Clarence Thompson, Zachary Smith | 2010-10-19 |
| 7574341 | Speculative expectation based event verification | Ryan Thompson, Zachary Smith | 2009-08-11 |
| 7519865 | Systems and methods for identifying incomplete transactions | Ryan Clarence Thompson, Zachary Smith | 2009-04-14 |
| 7313731 | Systems and methods for identifying erroneous transactions | Zachary Smith, Ryan Clarence Thompson | 2007-12-25 |
| 7219345 | System and method for terminating processes in a distributed computing system | Ryan Clarence Thompson | 2007-05-15 |
| 7210111 | Systems and methods for conducting future signal checks | Zachary Smith, Ryan Clarence Thompson | 2007-04-24 |
| 7200542 | Method and apparatus for biased identification of potential data sharing locations | Ryan Clarence Thompson | 2007-04-03 |
| 7103812 | Method and apparatus for tracking memory access statistics for data sharing applications | Ryan Clarence Thompson | 2006-09-05 |
| 7065603 | Virtual bus interface production of header-type fields from data-type fields | Zachary Smith, Ryan Clarence Thompson | 2006-06-20 |
| 7051301 | System and method for building a test case including a summary of instructions | Ryan Clarence Thompson, Adam Brown | 2006-05-23 |
| 6986110 | Automated method and system for backtracing of instruction parameters from specified instruction in test cases | Ryan Clarence Thompson | 2006-01-10 |
| 6968428 | Microprocessor cache design initialization | Ryan Clarence Thompson | 2005-11-22 |
| 6963997 | Transaction logging and intelligent error reporting in an expectation-based memory agent checker | Adam Brown, Zachary Smith | 2005-11-08 |
| 6845440 | System for preventing memory usage conflicts when generating and merging computer architecture test cases | Ryan Clarence Thompson | 2005-01-18 |
| 6735746 | Method and apparatus for TLB entry tracking, collision detection, and address reassignment, in processor testcases | Ryan Clarence Thompson | 2004-05-11 |