Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9286184 | Probabilistic correlation of system events with program instructions | — | 2016-03-15 |
| 8516226 | Executing a prefetching policy responsive to entry into an execution phase of an application | Norman Paul Jouppi | 2013-08-20 |
| 8392900 | Methods and systems for barrier reduction in parallel processing systems | Robert Schreiber | 2013-03-05 |
| 8364874 | Prioritized polling for virtual network interfaces | Michael Schlansker, Rajendra Kumar | 2013-01-29 |
| 8185697 | Methods and systems for coherence protocol tuning | Sami Yehia | 2012-05-22 |
| 7984242 | Program thread syncronization | Norman Paul Jouppi, Michael Schlansker | 2011-07-19 |
| 7962656 | Command encoding of data to enable high-level functions in computer networks | Boon Seong Ang, Michael Schlansker, Robert Schreiber, Norman Paul Jouppi | 2011-06-14 |
| 7912998 | DMA access systems and methods | Michael Schlansker, Erwin Oertli | 2011-03-22 |
| 7757237 | Synchronization of threads in a multithreaded computer program | Alan H. Karp | 2010-07-13 |
| 7673296 | Method and system for optional code scheduling | Alan H. Karp | 2010-03-02 |
| 7650471 | Head of queue cache for communication interfaces | Michael Schlansker, Erwin Oertli | 2010-01-19 |
| 7617495 | Resource-aware scheduling for compilers | Kalyan Muthukumar, Daniel Lavery, Gerolf F. Hoflehner, Chu-Cheow Lim | 2009-11-10 |
| 7587555 | Program thread synchronization | Norman Paul Jouppi, John Morgan Sampson | 2009-09-08 |
| 7555607 | Program thread syncronization for instruction cachelines | Norman Paul Jouppi, Michael Schlansker | 2009-06-30 |
| 7366956 | Detecting data races in multithreaded computer programs | Alan H. Karp | 2008-04-29 |
| 7302680 | Data repacking for memory accesses | Kalyan Muthukumar | 2007-11-27 |
| 7296136 | Methods and systems for loading data from memory | Robert Schreiber, Michael Schlansker | 2007-11-13 |
| 7206920 | Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements | — | 2007-04-17 |
| 7100157 | Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor | — | 2006-08-29 |