Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7143374 | System and method for achieving analysis capacity for circuit analysis tools | S. Brandon Keller, George Harold Robbert | 2006-11-28 |
| 7134107 | System and method for determining detail of analysis in a circuit design | S. Brandon Keller, George Harold Robbert | 2006-11-07 |
| 7124393 | System and method for processing configuration information | S. Brandon Keller, George Harold Robbert | 2006-10-17 |
| 7124380 | System and method for controlling analysis of multiple instantiations of circuits in hierarchical VLSI circuit designs | S. Brandon Keller, George Harold Robbert | 2006-10-17 |
| 7086019 | Systems and methods for determining activity factors of a circuit design | S. Brandon Keller, George Harold Robbert | 2006-08-01 |
| 7076752 | System and method for determining unmatched design elements in a computer-automated design | S. Brandon Keller, George Harold Robbert | 2006-07-11 |
| 7073152 | System and method for determining a highest level signal name in a hierarchical VLSI design | S. Brandon Keller, George Harold Robbert | 2006-07-04 |
| 7062727 | Computer aided design systems and methods with reduced memory utilization | S. Brandon Keller, George Harold Robbert | 2006-06-13 |
| 7058908 | Systems and methods utilizing fast analysis information during detailed analysis of a circuit design | S. Brandon Keller, George Harold Robbert | 2006-06-06 |
| 7047507 | System and method for determining wire capacitance for a VLSI circuit | S. Brandon Keller, George Harold Robbert | 2006-05-16 |
| 7032206 | System and method for iteratively traversing a hierarchical circuit design | S. Brandon Keller, George Harold Robbert | 2006-04-18 |
| 6957367 | System and method for controlling activity of temporary files in a computer system | S. Brandon Keller, George Harold Robbert | 2005-10-18 |
| 6944552 | System and method for detecting power deficiencies in a computer component | Erin Francom | 2005-09-13 |
| 6637012 | Method and system for identifying FETs implemented in a predefined logic equation | S. Brandon Keller | 2003-10-21 |
| 6618840 | Method and system for analyzing a VLSI circuit design | S Brandon Keller, Charles Lelm | 2003-09-09 |
| 6606733 | Method and system for finding static NAND and NOR gates within a circuit and identifying the constituent FETs each gate | S Brandon Keller | 2003-08-12 |
| 6550040 | Method and system for identifying dynamic NAND or NOR gates from a netlist | S. Brandon Keller | 2003-04-15 |
| 6536021 | Method and system for representing hierarchical extracted resistance-capacitance files of a circuit model | S Brandon Keller | 2003-03-18 |
| 6502223 | Method for simulating noise on the input of a static gate and determining noise on the output | S Brandon Keller | 2002-12-31 |
| 6496031 | Method for calculating the P/N ratio of a static gate based on input voltages | S Brandon Keller | 2002-12-17 |