| 5561429 |
Content limit addressable memory |
M. Halberstam, James E Meister, Dennis A. Henlin, Jun-ichi Sano, Edward T. Lewis |
1996-10-01 |
| 4901285 |
High density read-only memory |
Jun-ichi Sano, Lance Glasser |
1990-02-13 |
| 4866658 |
High speed full adder |
Dennis A. Henlin, Edward T. Lewis |
1989-09-12 |
| 4704701 |
Conditional carry adder for a multibit digital computer |
Edward T. Lewis |
1987-11-03 |
| 4675838 |
Conditional-carry adder for multibit digital computer |
Edward T. Lewis |
1987-06-23 |
| 4599704 |
Read only memory circuit |
— |
1986-07-08 |
| 4589008 |
Apparatus for electrically joining the ends of substantially parallel semiconductor lines |
Roger G. Stewart |
1986-05-13 |
| 4521695 |
CMOS D-type latch employing six transistors and four diodes |
William E. Engeler |
1985-06-04 |
| 4506349 |
Cross-coupled transistor memory cell for MOS random access memory of reduced power dissipation |
William E. Engeler |
1985-03-19 |
| 4499558 |
Five-transistor static memory cell implemental in CMOS/bulk |
William E. Engeler |
1985-02-12 |
| 4484087 |
CMOS latch cell including five transistors, and static flip-flops employing the cell |
William E. Engeler |
1984-11-20 |
| 4484088 |
CMOS Four-transistor reset/set latch |
William E. Engeler |
1984-11-20 |
| 4472821 |
Dynamic shift register utilizing CMOS dual gate transistors |
William E. Engeler |
1984-09-18 |
| 4468574 |
Dual gate CMOS transistor circuits having reduced electrode capacitance |
William E. Engeler |
1984-08-28 |
| 4423432 |
Apparatus for decoding multiple input lines |
Roger G. Stewart |
1983-12-27 |
| 4419741 |
Read only memory (ROM) having high density memory array with on pitch decoder circuitry |
Roger G. Stewart |
1983-12-06 |
