Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8637387 | Layout design method and semiconductor integrated circuit | — | 2014-01-28 |
| 8584069 | Apparatus and method for design support using layout positions of first and second terminals | Shigenori Ichinose, Kenji Suzuki, Kenji Kumagai, Takafumi Miyahara, Shuji Tanahashi +1 more | 2013-11-12 |
| 8468485 | Integrated circuit, integrated circuit design device and integrated circuit design method | — | 2013-06-18 |
| 8448125 | Method and apparatus for checking current density limitation | — | 2013-05-21 |
| 8291362 | Design support program, design support device, and design support method | — | 2012-10-16 |
| 7913212 | Method for determining a length of shielding of a semiconductor integrated circuit wiring | Shigenori Ichinose | 2011-03-22 |
| 7836415 | Circuit design method and circuit design system for calculating power consumption considering IR-drop | — | 2010-11-16 |
| 7784001 | Circuit design method, circuit design system, and program product for causing computer to perform circuit design | Shuji Tanahashi | 2010-08-24 |
| 7519926 | Semiconductor device and method for designing the same | — | 2009-04-14 |
| 7401308 | Timing analysis apparatus, timing analysis method, and computer product | Hisayoshi Oba | 2008-07-15 |
| 7361975 | Semiconductor integrated circuit having reduced cross-talk noise | Shigenori Ichinose | 2008-04-22 |
| 7339250 | Semiconductor integrated circuit having reduced cross-talk noise | Shigenori Ichinose | 2008-03-04 |
| 6972493 | Semiconductor integrated circuit having reduced cross-talk noise | Shigenori Ichinose | 2005-12-06 |
| 6968521 | Method, apparatus and program product for automatic placement and routing of integrated circuit | Shigenori Ichinose, Kouji Banno | 2005-11-22 |
| 6960793 | Semiconductor integrated circuit | — | 2005-11-01 |
| 6664638 | Semiconductor integrated circuit having reduced cross-talk noise | Shigenori Ichinose | 2003-12-16 |